Responsible for the overall design of digital logic blocks for mixed signal data communications product from architectural specification, RTL design, block level verification, synthesis, timing constraints – through full-chip sign-off. Responsibilities also include supporting design verification and backend to tape out of the full chip.
B.Sc. in Electrical Engineering from known university
Minimum 5 years of experience in logic design using Verilog
Experienced with architecture, specs, documentation, coding in Verilog and debugging