BSc in Electronics engineering/communication system engineer/ Computer Engineering.
Language Knowledge: Verilog and system Verilog
2-4 years of experience as a VLSI Designer – including writing and ownership on a complex Verilog blocks for ASIC with tight frequency, area and power requirements. Working
2-4 years of experience as a VLSI design team leader – including managing 3-5 engineers in a tightly schedule high complexity design through the entire VLSI flowon a full design flow from high-level architecture definitions, through micro ARCH , Verilog writing and verification process up to timing closure and STA