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Tag Archives: system verilog

Synthesis DFT and STA Engineer

BSc in Electrical Engineering.
3 – 5 years of experience running large scale synthesis and static timing analysis in deep submicron design technologies.
Experience with design flows utilizing Unix, Linux and Verilog / System Verilog
Good knowledge and experience of working with Cadence and/or Mentor Syn/DFT tools
Excellent knowledge of working with IPs integration and related views (.Lib, ATPGLib, CTL, UPF, etc…)
Expertise in scripting skills in Perl, TCL/TK, and C shell.
Capable of assisting in determining methods and procedures to use on new projects and new design.
Candidate must possess passion and commitment for completing projects on time.

Logic Verification Engineer

BSc in Electrical Engineering, from a well-known university.
2 – 4 years of experience in full chip and block level logic verification
Experience in Verilog and System Verilog coding
Candidate must possess passion and commitment for completing projects on time.