„Taking part in the architecture and implementation of complex Satellite MAC layer, Networking and SoC IPs
„Working closely with architecture team developing together high end DSP and Networking IPs
Responsible for the correctness and timing closure of the IP
Job Requirements
BSc in Computer science/ Electrical engineering from a known University with grade average greater than 85
Strong background in signal processing and/or communications protocols – Must
AT least 5 years experience as VLSI Design Eng with Verilog- Must
Experience with synthesis and STA -Advantage
