Logic Verification Engineer

BSc in Electrical Engineering, from a well-known university.
5-12 years of experience in full chip and block level logic verification. SOC Architecture design and implementation knowledge is an advantage. Working experience with
Strong verification skills including a good knowledge and understanding of different verification methodologies (random vs. directed testing, fullchip vs. module-level)
Working knowledge and experience with Verilog
MCU/Flash products – advantage.