” Circuit Design Engineers with 5+ years of experience.
” Proficiency in designing high speed digital circuitry integrated in analog blocks – dynamic logic, shift registers, serializer, clock dividers
” CMOS design experience and experience with Cadence tools are required.
” Experienced with pre/post layout Spice simulations
” Past experience in high speed clocking / standard cells / SRAM array can be relevant
” Experience with one of the following will be considered an advantage: RTL, Backend tools (Synthesis, P&R), Mixed Signal IC